MT47H32M16 – (MT47HxxxMx) DDR2 SDRAM

MT47H32M16 Datasheet PDF learn more.

Part number : MT47H32M16

Functions : This is a kind of semiconductor, (MT47HxxxMx) DDR2 SDRAM.

Pin arrangement :

Package information :

Manufacturer : Micron Technology

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MT47H32M16 Datasheet PDF

The texts in the PDF file :

512Mb: x4, x8, x16 DDR2 SDRAM

Features

DDR2 SDRAM MT47H128M4 – 32 Meg x 4 x 4 banks MT47H64M8 – 16 Meg x 8 x 4 banks MT47H32M16 – 8 Meg x 16 x 4 banks For the latest data sheet, refer to Micron’s Web site: http://www.micron.com/ddr2

Features

• • • • • • • • • • • • • • • • • RoHS compliant VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V JEDEC standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option 4-bit prefetch architecture Duplicate output strobe (RDQS) option for x8 DLL to align DQ and DQS transitions with CK 4 internal banks for concurrent operation Programmable CAS latency (CL) Posted CAS additive latency (AL) WRITE latency = READ latency – 1 tCK Programmable burst lengths: 4 or 8 Adjustable data-output drive strength 64ms, 8,192-cycle refresh On-die termination (ODT) Industrial temperature (IT) option Supports JEDEC clock jitter specification Options • Configuration 128 Meg x 4 (32 Meg x 4 x 4 banks) 64 Meg x 8 (16 Meg x 8 x 4 banks) 32 Meg x 16 (8 Meg x 16 x 4 banks) • FBGA package (lead-free) 84-ball FBGA (12mm x 12.5mm) (:B) (10mm x 12.5mm) (:D) 60-ball FBGA (12mm x 10mm) (:B) (10mm x 10mm) (:D) • Timing – cycle time 5.0ns @ CL = 3 (DDR2-400) 3.75ns @ CL = 4 (DDR2-533) 3.0ns @ CL = 5 (DDR2-667) 3.0ns @ CL = 4 (DDR2-667) 2.5ns @ CL = 6 (DDR2-800) 2.5ns @ CL = 5 (DDR2-800) • Self refresh Standard Low-power • Operating temperature Commercial (0°C ≤ TC ≤ 85°C) Industrial (–40°C ≤ TC ≤ 95°C; –40°C ≤ TA ≤ 85°C) • Revision Marking 128M4 64M8 32M16 CC BN CB B6 -5E -37E -3 -3E -25 -25E None L None IT :A/:B/:D Table 1: Architecture Configuration Addressing 128 Meg x 4 64 Meg x 8 32 Meg x 16 16 Meg x 8 x 4 banks 8K 16K (A0–A13) 4 (BA0–BA1) 1K (A0–A9) 8 Meg x 16 x 4 banks 8K 8K (A0–A12) 4 (BA0–BA1) 1K (A0–A9) Table 2: Key Timing Parameters tRC (ns) Configuration 32 Meg x 4 x 4 banks 8K Refresh Count 16K (A0–A13) Row Addr. 4 (BA0 [ … ]

MT47H32M16 PDF File



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