H27U2G8F2C – 2Gb NAND FLASH

H27U2G8F2C Datasheet PDF learn more.

Part number : H27U2G8F2C

Functions : This is a kind of semiconductor. 2Gb NAND FLASH.

Pin arrangement :

Package information :

Manufacturer : Hynix

Image :

H27U2G8F2C Datasheet PDF

The texts in the PDF file :

APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 1 H27(U_S)2G8_6F2C 2 Gbit (256M x 8 bit) NAND Flash 2Gb NAND FLASH H27U2G8_6F2C H27S2G8_6F2C Rev 0.0 / Apr. 2010 1 *da93e538-013c* B34416/177.179.157.84/2010-06-28 11:19 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 1 H27(U_S)2G8_6F2C 2 Gbit (256M x 8 bit) NAND Flash Document Title 2 Gbit (256M x 8 bit) NAND Flash Memory Revision History Revision No. 0.0 0.1 History Initial Draft Add FBGA Package Draft Date Apr. 19. 2010 May. 28. 2010 Remark Preliminary Rev 0.0 / Apr. 2010 2 *da93e538-013c* B34416/177.179.157.84/2010-06-28 11:19 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 1 H27(U_S)2G8_6F2C 2 Gbit (256M x 8 bit) NAND Flash FEATURES SUMMARY DENSITY – 2Gbit: 2048blocks Nand FLASH INTERFACE – NAND Interface – ADDRESS / DATA Multiplexing SUPPLY VOLTAGE – Vcc = 3.0/1.8V Volt core supply voltage for Program, Erase and Read operations. MEMORY CELL ARRAY – X8: (2K + 64) bytes x 64 pages x 2048 blocks – X16: (1k+32) words x 64 pages x 2048 blocks PAGE SIZE – X8: (2048 + 64 spare) bytes – X16:(1024 + 32spare) Words Block SIZE – X8: (128K + 4K spare) bytes – X16:(64K + 2K spare) Words PAGE READ / PROGRAM – Random access: 25us (Max) – Sequential access: 25ns / 45ns (3.0V/1.8V, min.) – Program time(3.0V/1.8V): 200us / 250us (Typ) – Multi-page program time (2 pages): 200us / 250us (3.0V/1.8V, Typ.) BLOCK ERASE / MULTIPLE BLOCK ERASE – Block erase time: 3.5 ms (Typ) – Multi-block erase time (2 blocks): 3.5ms/ 3.5ms (3.0V/1.8V, Typ.) SEQURITY – OTP area – Sreial number (unique ID) – Non-volatile protection option for OTP and Block0(Opt.) – Hardware program/erase disabled during power transition ADDTIONAL FEATURE – Multiplane Architecture: Array is split into two independent planes. Parallel operations on both planes are available, having program and erase time. – Single and multiplane copy back program with automatic EDC (error detect [ … ]

H27U2G8F2C PDF File



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